1. Field of the Invention
This invention relates to a novel host bus interface, and more particularly to a host bus interface which allows compatibility with older ISA bus standard I/O devices.
2. Discussion of Background
In recent years, high performance personal computers (PCs) have been introduced into the market. These newer high performance PCs are typically much faster than older (also referred to as "legacy") computers such as IBM XT/AT PCs. The newer high performance PCs may be based on CPU's, such as the 80486, Pentium, etc., which can typically operate at speeds much greater than the CPUs of the XT/AT legacy computers, such as the 8186, 8088, 80286, etc. In addition, the newer high performance PCs typically include a high speed peripheral bus, such as a PCI bus, VESA bus, etc., which can typically operate at speeds much greater than the peripheral bus of the XT/AT legacy computers, such as an ISA bus, EISA bus, etc. There are many existing hardware peripherals and software developed for the ISA bus of the XT/AT legacy PCs, and accordingly, it is desirable for these newer high performance PCs to provide compatibility with peripherals and software designed for the older XT/AT PCs having an ISA bus.
For a newer high performance PC (e.g., based on the 80486 or Pentium CPU, etc.), the above-stated problem may be solved using the configuration shown in FIG. 7. FIG. 7 shows the minimal circuitry required to understand the host bus interface according to the background art invention, although it is to be understood that the PC may include other system devices (which are not shown), such as memories, disk drives, clock generators, monitors, speakers, motherboard, other peripherals, etc., as will be apparent to those skilled in the computer arts.
In FIG. 7, a CPU 2 (e.g., based on the 80486 or Pentium CPU, etc.) is coupled to a host bus 3 via signal lines 2a. A host bus bridge (north bridge) 4 is coupled to the host bus 3 via signal lines 4a. The north bridge 4 provides an interface to PCI bus 6 via signal lines 4b. Also coupled to the PCI bus 6 via signal lines 8a is an ISA-to-PCI bridge (south bridge) 8. The south bridge 8 is also coupled to an ISA bus 10 via signal lines 8b. With the above architecture, CPU 2 is able to perform I/O transactions between the CPU 2 and legacy I/O devices located within the south bridge 8. These legacy I/O devices located in south bridge 8 may provide various functions to peripheral devices connected to the ISA bus 10 and to other system devices of an XT/AT ISA bus PC.
The PCI bus 6 is a newer high speed peripheral bus, such as a 32-bit or 64-bit bus running at 25 MHz or 33 MHz, etc. The ISA bus 10 is an older slower peripheral bus, such as an 8-bit or 16-bit bus running at 8 MHz or 8.33 MHz, etc. The north bridge 4 is a controller chip that typically bridges the CPU 2 and other system resources of the PC (which are not shown), such as DRAM, cache memory, post write buffer, etc. The south bridge 8 is a controller chip that bridges the legacy ISA bus 10 to the faster PCI bus 6 and the north bridge 4. As previously discussed, the south bridge 8 also hosts legacy I/O devices which provide various functions to peripheral devices connected to the ISA bus 10 and which will now be described with reference to FIG. 8.
FIG. 8 shows details of an internal structure of south bridge 8. In FIG. 8, south bridge 8 includes legacy PCI/ISA controller 12 coupled to signal lines 8a which provide an interface to the PCI bus 6. The PCI/ISA controller 12 is also coupled to signal lines 8b (SD-BUS) which provide an interface to the ISA bus 10. Buffer 14 is coupled to SD-BUS 8b via signal lines 14b. Direct Memory Access (DMA) controller 16, such as an Intel 82C37A CHMOS Programmable DMA controller, interrupt controller 18, such as an Intel 82C59A CHMOS Programmable Interrupt Controller, timer/counter 20, such as an Intel 82C54 CHMOS Programmable Interval Timer, and real time clock 22, such as a Dallas Semiconductor DS 1287 Real Time Clock, are coupled to buffer 14 via signal lines 14a (XD-BUS). The operation of south bridge 8 will now be described.
The PCI/ISA controller 12 provides an interface from the PCI bus 6 to the DMA controller 16, the interrupt controller 18, the timer/counter 20, and the real time clock 22 via buffer 14. The DMA controller 16 provides peripheral devices connected to the ISA bus 10 direct access to the main memory of the PC, thereby freeing the CPU 2 from performing simple but time-consuming data transfers. The interrupt controller 18 manages and prioritizes hardware interrupt requests from peripheral devices connected to the ISA bus 10 and passes the prioritized hardware interrupts to the CPU 2. There are two basic types of hardware interrupts processed by the interrupt controller 18: non-maskable interrupts (NMI) and maskable interrupt requests (IRQ). The timer/counter 20 is a programmable interval timer (PIT) having three independent programmable counters (0, 1 and 2, not shown). The counter 0, for example, is used for periodically updating the PC's internal system clock, the counter 1, for example, is used for periodically activating the PC's memory refresh function, and the counter 2, for example, is used for generating tone frequencies for the PC's speaker. The real time clock 22 is a battery-backed-up timer that keeps a current date and time for the PC regardless of whether the PC is turned on or off. The XD-BUS 14a is a low speed bus defined in the XT/AT PC architecture, and is used by several legacy I/O devices including the DMA controller 16, the interrupt controller 18, the timer/counter 20 and the real time clock 22. These legacy I/O devices, for example, are important for the compatibility of the newer PC designs with software and peripheral hardware designed for the legacy XT/AT ISA bus PCs.
With the above architecture, the CPU 2 accesses the XD-BUS 14a legacy I/O devices by starting I/O transactions on the host bus 3 via the signal lines 2a (FIG. 7). Typically, the CPU 2 is running at 60 or 66 MHz (i.e., 60 or 99 ns clock cycles) and therefore, ideally, the I/O transactions should be completed in as few CPU 2 clock cycles as possible. However, the I/O transactions have to pass through the north bridge 4 and then the south bridge 8 before access to the legacy I/O devices within south bridge 8 can be completed (FIG. 7). At the south bridge 8, the I/O transactions are running at a standard ISA bus timing of, for example, 8 MHz or 8.33 MHz. As a result, a standard 16-bit ISA I/O transaction typically requires a minimum of 375 ns to complete (3 ISA clock cycles at 8 MHz). However, I/O transactions directed towards the interrupt controller 18, the timer/counter 20 and the real time clock 22 are usually 8-bit ISA I/O transactions which require additional ISA clock cycles to complete as compared to the 16-bit ISA I/O transactions. In addition, time is needed for the south bridge 8 to arbitrate for the PCI bus 6 and the ISA bus 10. Therefore in more typical cases the I/O transactions directed towards these legacy I/O devices require in the range of 1.5 microseconds to complete, as seen from the CPU 2 side. When access to these legacy I/O devices is frequent, the CPU 2 is slowed down, which thereby adversely impacts the overall system performance.
The background art configuration of FIG. 7 therefore has several disadvantages including requiring to perform I/O transactions to access legacy I/O devices (e.g., the DMA controller 16, the interrupt controller 18, the timer/counter 20 and the real time clock 22) located in the south bridge 8 at the ISA bus timing of 8 MHz or 8.33 MHz, which thereby adversely impacts the overall system performance when accesses to these legacy I/O devices by the CPU 2 are frequent.